ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 1 ? 2000-2002, 2005, 2007 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimer s are as listed at http://www.xilinx.com/legal.htm . powerpc is a trademark of ibm, inc. all other trademarks are t he property of their respective owners. all specifications are su bject to change without notice. features ? configuration one-time programmable (otp) read-only memory designed to store configuration bitstreams for spartan?-ii/spartan-iie fpga devices ? simple interface to the spartan device ? programmable reset polarity (active high or active low) ? low-power cmos floating gate process ? 3.3v prom ? available in compact plastic 8-pin dip, 8-pin voic, 20-pin soic, or 44-pin vqfp packages ? programming support by leading programmer manufacturers ? design support using the xilinx alliance and foundation? series software packages ? guaranteed 20-year life data retention ? pb-free (rohs-compliant) packaging available introduction the xc17s00a family of proms provide an easy-to-use, cost-effective method for storing spartan-ii/spartan-iie device configuration bitstreams. when the spartan device is in master serial mode, it generates a configuration clock that drives the spartan prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the spartan device d in pin. the spartan device generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when a spartan device is in slave serial mode, the prom and the spartan device must both be clocked by an incoming signal. for device programming, either the xilinx alliance or the spartan device design file into a standard hex format which is then transferred to most commercial prom programmers. 0 spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 05 product specification r spartan-ii/iie fpga configuration bits compatible spartan-ii/iie prom xc2s15 197,696 xc17s15a xc2s30 336,768 xc17s30a xc2s50 559,200 xc17s50a xc2s100 781,216 xc17s100a xc2s150 1,040,096 xc17s150a xc2s200 1,335,840 xc17s200a xc2s50e 630,048 xc17s50a xc2s100e 863,840 xc17s100a xc2s150e (1) 1,134,496 xc17s200a xc2s200e 1,442,016 xc17s200a xc2s300e 1,875,648 xc17s300a xc2s400e 2,693,440 xc17v04 (2) xc2s600e 3,961,632 xc17v04 (2) notes: 1. due to the higher configuration bit requirements of the xc2s1 50e device, an xc17s200a prom is required to configure this fpga . 2. see xc17v00 series configuration proms data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 2 r pin description pins not listed are no connects. pinout diagrams pin name 8-pin pdip (pd8/pdg8) and voic/tsop (vo8/vog8) 20-pin soic (so20) 44-pin vqfp (vq44) pin description data 1 1 40 ? data output, high-z state when either ce or oe are inactive. during programming, the data pin is i/o. note that oe can be programmed to be either active high or active low. clk 2 3 43 ? each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe (oe/reset ) 3813 ? when high, this input holds the address counter reset and puts the data output in a high-impedance state. the polarity of this input pin is programmable as either reset/oe or oe/reset . to avoid confusion, this document describes the pin as reset/oe , although the opposite polarity is possible on all devices. when reset is active, the address counter is held at zero, and the data output is in a high-impedance state. the polarity of this input is programmable. the default is active- high reset, but the preferred option is active low reset , because it can be connected to the fpgas init pin and a pull-up resistor. ? the polarity of this pin is controlled in the programmer interface. this input pin is easily inverted using the xilinx hw-130 programmer software. third-party programmers have different methods to invert this pin. ce 41015 ? when high, this pin resets the internal address counter, puts the data output in a high-impedance state, and forces the device into low-i cc standby mode. gnd 5 11 18, 41 ? gnd is the ground connection. v cc 7, 8 18, 20 38, 35 ? the v cc pins are to be connected to the positive voltage supply. pd8/pdg8 vo8/vog8 top view ds078_04_061805 8 7 6 5 1 2 3 4 vcc vcc nc gnd data (d0) clk oe/reset ce ds078_05_061805 so20 top view 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 data(d0) nc clk nc nc nc nc oe/reset nc ce vcc nc vcc nc nc nc nc nc nc gnd 1 2 3 4 5 6 7 8 9 10 11 vq44 top view nc nc nc nc nc nc nc nc nc nc nc nc oe/reset nc ce nc nc gnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc clk nc gnd data(d0) nc vcc nc nc vcc nc ds073_06_061805 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 3 r controlling proms ? connecting the spartan device with the prom: ? the data output of the prom drives the d in input of the lead spartan device. ? the master spartan device cclk output drives the clk input of the prom. ? the reset /oe input of the prom is connected to the init pin of the spartan device and a pull-up resistor. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. ? the ce input of the prom is connected to the done pin of the spartan device and a pull-up resistor. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the spartan device mode pins. in master serial mode, the spartan device automatically loads the configuration program from an external memory. the xc17s00a prom has been designed for compatibility with the master serial mode. upon power-up or reconfiguration, the spartan device enters the master serial mode when the mode pins are set to master serial mode. data is read from the prom sequentially on a single data line. synchronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration interface ( figure 1 ). only a serial data line, two control lines, and a clock line are required to configure the spartan device. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function d in pin on the spartan device is used only for configuration, it must still be held at a defined level during normal operation. the spartan-ii/spartan-iie family takes care of this automatically with an on-chip pull-up/down resistor or keeper circuit. the one-time-programmable xc17s00a prom in figure 1, page 3 supports automatic loading of configuration programs. an early done inhibits the prom data output one cclk cycle before the spartan fpga i/os become active. figure 1: xc17s00a prom connections to fpga in master serial mode d in cclk init done xc17 s 00a prom data clk ce s partan-ii/ s partan-iie ma s ter s erial d s 07 8 _01_061107 oe/re s et m0 m1 m2 3 . 3 v v cc v cc 3 . 3 v 3 . 3 k note s : 1. if the drivedone config u r a tion option i s not a ctive, p u ll u p done with a 3 . 3 k re s i s tor. 3 . 3 k
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 4 r standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high-impedance state regardless of the state of the oe input. programming spartan-ii/spartan-iie family proms the devices can be programmed on programmers supplied by xilinx or qualified third-pa rty vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. caution! always tie the two v cc pins together. figure 2: simplified block diagram (does not show programming circuit) ta bl e 1 : truth table for xc17s00a control inputs control inputs internal address (2) outputs reset (1) ce data i cc inactive low if address < tc: increment if address > tc: don?t change active high-z active reduced active low held reset high-z active inactive high not changing high-z standby active high held reset high-z standby notes: 1. the xc17s00a rese t input has programmable polarity 2. tc = terminal count = highest address value. tc + 1 = address 0. eprom cell matrix address counter ce data oe output clk v cc gnd ds030_02_011300 tc oe reset/ oe/ reset or
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 5 r xc17s15a, xc17s30a, xc 17s50a, xc17s100a, xc17s 150a, xc17s200a, and xc17s300a absolute maximum ratings (1) operating conditions (1) dc characteristics over operating condition symbol description value units v cc supply voltage relative to gnd ?0.5 to +4.0 v v in input voltage with respect to gnd ?0.5 to v cc +0.5 v v ts voltage applied to high-z output ?0.5 to v cc +0.5 v t stg storage temperature (ambient) ?65 to +150 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. symbol description min max units v cc commercial supply voltage relative to gnd (t a = 0 c to +70 c) 3.0 3.6 v industrial supply voltage relative to gnd (t a = ?40 c to +85 c) 3.0 3.6 v t vcc v cc rise time from 0v to nominal voltage 1.0 50 ms notes: 1. during normal read operation, both v cc pins must be connected together. 2. at power-up, the device requires the v cc power supply to monotonically rise from 0v to nominal voltage within the specified v cc rise time. if the power supply cannot meet this requirement, then the device may not perform a power-on-reset properly. symbol description min max units v ih high-level input voltage 2.0 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ?3 ma) 2.4 ? v v ol low-level output voltage (i ol = +3 ma) ? 0.4 v i cca supply current, active mode (at maximum frequency) ? 15 ma i ccs supply current, standby mode ? 1 m i l input or output leakage current ?10 10 a c in input capacitance (v in = gnd, f = 1.0 mhz) ? 10 pf c out output capacitance (v in = gnd, f = 1.0 mhz) ? 10 pf
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 6 r ac characteristics over operating condition (1) symbol description min max units t oe reset/oe to data delay ? 45 ns t ce ce to data delay ? 60 ns t cac clk to data delay ? 80 ns t oh data hold from ce , reset/oe , or clk (2) 0?ns t df ce or reset/oe to data float delay (2,3) ?50ns t cyc clock periods 100 ? ns t lc clk low time (2) 50 ? ns t hc clk high time (2) 50 ? ns t sce ce setup time to clk (to guarantee proper counting) 25 ? ns t hce ce hold time to clk (to guarantee proper counting) 0 ? ns t hoe reset/oe hold time (guarantees counters are reset) 25 ? ns t ceh ce high time (guarantees counters are reset) 20 ? ns notes: 1. ac test load = 50 pf 2. guaranteed by design, not tested. 3. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t ceh high < 2 s, t ce = 2 s. 6. if t hoe high < 2 s, t ce = 2 s. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds030_03_111502 t cyc t ceh
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 7 r ordering information 3.3v valid ordering combinations xc17s15apd8c xc17s50apd8c xc17s150apd8c xc17s15avo8c XC17S50APDG8C xc17s150avo8c xc17s15avog8c xc17s50avo8c xc17s150aso20c xc17s15aso20c xc17s50avog8c xc17s150apd8i xc17s15apd8i xc17s50aso20c xc17s150avo8i xc17s15avo8i xc17s50apd8i xc17s150aso20i xc17s15aso20i xc17s50avo8i xc17s50aso20i xc17s30apd8c xc17s100apd8c xc17s200apd8c xc17s30avo8c xc17s100avo8c xc17s200apdg8c xc17s30aso20c xc17s100 avog8c xc17s200avo8c xc17s30apd8i xc17s100aso20c xc17s200avog8c xc17s30avo8i xc17s100apd8i xc17s200apd8i xc17s30aso20i xc17s100avo8i xc17s200apdg8i xc17s100aso20i xc17s200avo8i xc17s200avog8i xc17s200avq44c xc17s200avq44i xc17s300avq44c xc17s300avq44i xc17s15a vo8 c operating range/processing c=commercial (t a = 0 c to +70 c) i=industrial (t a = ?40 c to +85 c) package type pd8/pdg8=8-pin plastic dip vo8/vog8=8-pin plastic small-outline thin package so20=20-pin plastic small-outline package vq44=44-pin plastic quad flat package device number xc17s15a xc17s30a xc17s50a xc17s100a xc17s150a xc17s200a xc17s300a
spartan-ii/spartan-iie family otp configuration proms (xc17s00a) ds078 (v1.10) june 25, 2007 www.xilinx.com product specification 8 r marking information due to the small size of the prom package, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows. revision history the following table shows the revision history for this document. date revision revision 09/14/00 1.0 initial xilinx release. 11/13/00 1.1 updated configuration bits. 04/07/01 1.2 added to features: ?guaranteed 20 year life data retention?, removed ?programmi ng the fpga with counters? and related text. 06/20/01 1.3 revised figure 1 resistor values to match spartan-ii data sheet. 10/09/01 1.4 added note for unlisted pins, changed i cca and i ccs , and added power-on supply requirements and note regarding power-on reset. 11/15/01 1.5 updated for spartan-iie fpga family. 06/25/02 1.6 changed table 1, page 4 . 10/15/02 1.7 changed table 1, page 4 . added "pinout diagrams," page 2 . 11/18/02 1.8 added xc2s400e and xc2s600e to compat ible fpgas table. modified document title. 06/24/05 1.9 added pb-fre e information to the "pinout diagrams" , "ordering information" , "3.3v valid ordering combinations" , and "marking information" figures. removed t sol from the "absolute maximum ratings(1)" table. 06/25/07 1.10 ? updated format. ? added pb-free (rohs-compliant) packaging. ? timing diagram removed from figure 1, page 3 . ? part numbers xc17s200apdg8i, and xc17s200avog8i added to "3.3v valid ordering combinations," page 7 . 17s15a v c operating range/processing c=commercial (t a = 0 c to +70 c) i=industrial (t a = ?40 c to +85 c) package mark p=8-pin plastic dip v=8-pin plastic small-outline thin package s=20-pin plastic small-outline package vq=44-pin plastic quad flat package g=8-pin plastic small-outline thin package, pb free (rohs compliant) h=8-pin plastic dip, lead free device marking 17s15a 17s30a 17s50a 17s100a 17s150a 17s200a 17s300a
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